The invention relates generally to overload protection devices, and more particularly to those used in computer power bus lines, which power downstream electronic components and power management circuits.
Modern technologies have allowed more and more computers to be connected to one another by way of networking. In a typical network system, a hub is connected to a number of nodes, each of which may be connected to a number of sub-nodes. Moreover, each sub-node may be connected to additional sub-subnodes, and so on. In such a network system, power is typically distributed to the various nodes and sub-nodes, etc. One example of such network environment relates to the recent USB (Universal Serial Bus) standards, e.g., USB Organization, USB Specification, Rev. 1.0, Jan. 15, 1996.
In such a network system, each network node is monitored. Normal operation as well as fault conditions are constantly reported to a control circuit. When a fault condition, e.g., overload condition, occurs at one node or sub-node, it is important that any point of failure not affect the operation of the remaining portions of the network system. In other words, the failure must be localized and isolated in order to achieve high performance in a network system.
Various power bus line protection devices have been proposed. FIGS. 1 and 2 illustrate conventional power line protection devices. In FIG. 1, microcontroller 10 is coupled to, for example, a peripheral port 12 which includes a power line protection device 20. Protection device 20 includes a controller 22 and two electronic components, namely, a p-channel enhancement type field effect transistor (FET) 24 and a positive temperature coefficient (PTC) resistor 26 electrically coupled to FET 24.
Under normal conditions, FET 24 is in the on-state and power is supplied to a peripheral device (not shown) to which peripheral port 12 is coupled.
When a fault condition, e.g., overcurrent condition, occurs, a short circuit exists between node 29 and the ground and PTC resistor 26 heats up and trips (i.e., changes its resistance) to a very large resistance value. Thus, the output current flowing in PTC resistor 26 is limited. Upon sensing a low voltage at the OC (overcurrent) node, controller 22 informs microcontroller 10 of the fault condition, i.e., overcurrent condition. Then, microcontroller 10 instructs controller 22 to send a logic signal, via the PC (power control) node, to the gate of FET 24 to turn off FET 24.
The disadvantages of the circuit shown in FIG. 1 are that it has a long trip time, which puts strain on FET 24. Also, it has a larger physical size in order to meet the low resistance requirements for the FET, which thus increases the cost.
In FIG. 2, a dedicated power integrated circuit (IC) 30, which includes a FET 31 and a series resistor 33, is used in a power line protection device 32 in a peripheral port 12. When overload (or overcurrent) conditions occur, controller 26 receives the fault condition report from power IC 30, via the OC node, a high current at the output of power IC 30, and informs microcontroller 10 of the fault condition. Microcontroller 10 then instructs controller 26 to turn off power IC 30, via the node PC.
A main disadvantage of this circuit is cost because, for the same on-resistance, a power IC is more expensive than a vertical FET due to its lateral structure. In order to reduce power loss, it is necessary to minimize the overall resistance of the IC chip. In order to achieve the required low on5 resistance of the FET, a large silicon IC chip has to be used when coupling to the discrete device in FIG. 1. Therefore, the cost is high.